IBM says it can fit nearly 100 billion transistors on a chip - why the milestone matters

IBM unveiled a research chip architecture called NanoStack that it says is the world’s first sub-1-nanometer technology, shown at the 0.7 nm (7 angstrom) node. The design packs nearly 100 billion transistors onto a fingernail-size die, roughly doubling the density of IBM’s earlier 2-nm test chip; today’s most powerful chips top out at about 80 billion transistors.

NanoStack stacks and staggers nanosheet transistors vertically, bonding two nanosheet devices into a single structure with each tier optimized and contacted from opposite sides. Each transistor uses three sub-5 nm‑thick nanosheets — about 15 silicon atoms across — separated by roughly 9 nm spacers, with an ultra-thin dielectric bond joining the tiers.

IBM presents this as a platform that could scale through 7 Å, 5 Å, 3 Å and potentially 1 Å generations; an angstrom is one ten‑billionth of a meter.

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